Examples of conventional electron emitting devices of the type to which the present invention relates are disclosed in U.S. Pat. Nos. 3,755,704; 3,812,559; 4,857,161; 4,940,916; 5,194,780 and 5,225,820. The disclosures of those patents are incorporated herein by reference.
Microtip emission cathode structures usable in FED field emission flat-panel image display devices, as described in the referenced patents, typically comprise thin film metal/insulator/metal sandwich structures deposited on a glass or silicon support substrate. In a usual self-aligning method of fabrication, first and second conductive layers are deposited on the substrate, separated by an intervening dielectric insulating layer which functions to space and insulate the conductive layers. The bottom conductive layer functions as the emitting or cathode electrode. The top conductive layer functions as the extractor or gate electrode. Apertures are formed in the top conducting layer and in the intervening dielectric material, and a microtip emitter (sometimes called an electron field emitting spike, needle or protuberance) is formed within each aperture in electrical communication with the bottom conductive layer. Traditional designs have placed the emitters in either random or rectangular matrix arrays.
Early implementations formed the microtips directly on the lower or cathode electrode. Such arrangements, however, provided little protection against excessive current draw. The use of a resistive layer was therefore proposed to provide a ballast against excessive current in each microtip emitter, and consequently to homogenize the electron emission. The Borel, et al. '916 patent describes the use of a resistive layer above the cathode electrode and beneath the microtips. Such vertical resistor approach helps eliminate nonuniformity caused by excessively bright spots and reduces breakdown risk at the microtips by limiting current flow when local short-circuiting occurs between individual microtips and the gate. Under the Borel approach, however, when a short circuit occurs between a microtip and the gate, the full voltage applied between the gate and cathode conductors is applied vertically across the resistive coating. This requires the resistive coating to be thick enough to withstand the fulI gate-to-cathode voltage without breaking down due to heat. Thus, the existence of "pinhole" or other defects which locally reduce thickness of the resistive layer will lead to breakdown.
The Meyer '780 patent overcomes this deficiency by use of a lateral resistor cathode structure for a field emission device. A plurality of arrays of electrically conductive microtips are formed on a resistive layer, within respective mesh spacings of a conductive layer which is patterned into a mesh structure configuration. This arrangement provides an improvement in breakdown resistance of a field effect emissive device, without requiring increasing the thickness of the resistive layer. The mesh-like structure of the cathode conductor (and/or the gate conductor), permits the cathode conductor and the resistive coating to lie substantially in the same plane. In such configuration, the breakdown resistance is no longer susceptible to defects in the vertical thickness of the resistive coating, because it is the lateral separation of the microtips from the cathode conductor by the resistive coating which provides the ballast against excessive current. It is, therefore, sufficient to maintain a horizontal distance between the cathode conductor and the microtip which is adequate to prevent breakdown, while still retaining a homogenization effect for which the resistive coating is supplied.
In both the '916 and '780 approaches, the ballast is in the form of a resistive voltage drop, such that those microtips drawing the most current have the greatest resistive drop, thus acting in such a way as to limit microtip current. An equivalent circuit of the '916 or '780 ballast arrangement would have each tip in series with an individual buffer resistor to limit the field emission current. However, the ballast resistance between the microtips and the cathode conductor varies with the position of the individual microtip within the array. In a four-by-four rectangular matrix array, for example, a microtip in the corner of the array has a lower ballast resistance than a microtip at the side of the array, and a microtip in the side has a lower ballast resistance than a microtip in the interior. The difference in ballast resistance among microtips becomes even more pronounced as the size of the array or the spacing between microtips increases. Thus, an arrangement is desired which will enable all microtips to be substantially equal potential.